1. Field of the Invention
The present invention relates generally to computers and memory devices, and more particularly, to an apparatus and method for controlling data dispatch when multiple data requests are concurrently outstanding.
2. Description of the Related Art
Higher performance computers utilize hardware more efficiently to obtain greater throughput. In many cases, the processor speed is limited by the speed of transactions between the processor or another data requester and a memory device. Performance limitations involving the speed of data read or write transactions are commonly referred to as input/output (I/O) bottlenecks. An I/O bottleneck may slow the performance of a data requester when the requester must wait for the data requested before continuing to perform a task.
One method for mitigating the effects of I/O bottlenecks is to give higher priority to memory reads from data requesters with more critical or immediate needs. For example, memory read requests issued by a cache memory may be given a high priority, because the processor remains inactive until the data is returned to the cache memory. On the other hand, memory read requests from a graphics controller may be given a low priority, because the graphics controller can often request data in advance and can wait for the data during several cycles without becoming inactive. Prioritizing the processing of memory reads reduces the impact of I/O bottlenecks.
A priority arrangement for data requests increases the variability in the dispatch time for data requested by low priority requesters, because the processing of higher priority data requests introduces random delays into the processing time for lower priority requests. The uncertainty in the dispatch times creates problems when the low priority data requester issues several data requests concurrently. Then, the low priority requester will occasionally receive the data from two requests nearly simultaneously and may not be able finish processing the data from the first request quickly enough to setup and accept the data from the second request. The data for the second request may simply be lost when two requests are occasionally fulfilled substantially contemporaneously.
In the prior art, there are at least two approaches for addressing this problem. In the first approach, the low priority data requester does not issue a new data request until the data for all earlier requests has been received. When only one data request is outstanding, the dispatched data can be accepted and there is little risk that the requester will not be setup to receive the dispatched data. Unfortunately, waiting for each data read to be received before issuing a subsequent requests is inefficient. Such a method can slow the performance even of low priority requesters. In the second approach, the data retrieved for read requests is stored in one or more data buffers until the requesters are able to accept the data. Unfortunately, such data buffers may have to be large to accommodate occasional backlogs of dispatched data. The second approach may require substantial hardware that occupies a prohibitive area on a chip's die. In the prior art, prioritizing read requests often entails either slowing the lower priority data requesters or using substantial hardware for the data buffers that temporarily store the dispatched data.
The present invention is directed to overcoming, or at least to reducing the effects of, one or more of the problems set forth above.